Do you know why the MOSFET gate drive waveform oscillates? How to deal with it?

Do you know why the MOSFET gate drive waveform oscillates? How to deal with it?

In an ideal state when MOSFET, the MOSFET gate drive waveform is a relatively smooth pulse signal,

Ideal square wave Actual square wave

But the actual measured U waveform often oscillates, which can cause noise interference and additional power loss.

Do you know why the oscillation forms?

(As shown in the figure) order to provide sufficient drive current to the MOSFET, a push-pull circuit is generally used, such as transistors Q1 and Q2. There will be reactance and resistance in the actual circuit, as shown in the equivalent inductance L1 and equivalent resistance R1 in the figure, and there is a parasiticitance between the MOSFET GD and GS (equivalent to C1). L1 and C1 form a resonant oscillation circuit, because R1 is too small to play damping role, resulting in the formation of an oscillating waveform at the rising edge and falling edge of the drive pulse.

In order to suppress the oscillation, drive resistor is usually connected in series at the gate, and the resistor should be placed as close to the gate as possible when routing the PCB. The of the gate drive resistor has an effect on the oscillation:

When the gate is turned on and the drive resistor is too small (underdamped state, the oscillation cannot be suppressed;

When the value is too large (overdamped state), the MOSFET turn-on time is long and the loss is large.

Therefore, the most ideal is the critical damping state, at which time the gate drive resistor can suppress the oscillation without causing the MOS turn-on time to be prolonged.

At the same time, when designing the PCB, the gate connection routing should be as short and not bent to the oscillation of the drive pulse waveform and the value of the parasitic inductance.