Why does the MOSFET show a small plateau in Vgs?

Why does the MOSFET show a small plateau in Vgs?

Take an NMOS switch circuit as an example, where step signal VG1 sets the DC level to 2V and is a square wave with an amplitude of 2V and a frequency of 50Hz and the turn-on voltage of T2 is also 2V, which causes the MOSFET T2 to switch between the on and off states with a period 20ms.

During this process, an interesting phenomenon occurs: when Vgs = 2V, there is a small plateau. So, why there such a small plateau in Vgs when it rises?

The answer lies in the effect. There are various parasitic capacitances inside the MOSFET,where: Cgs is called the GS parasitic capacitance, Cgd is called the GD parasitic capacitance, the input capacitance Ciss = Cgs Cgd, the output capacitance Coss = Cgd   Cds, and the reverse transfer capacitance Crss = Cgd.

When the circuit working, the capacitance (Cgd), under the action of inverse amplification, will significantly increase the equivalent input capacitance value. When the input voltage is to Vgs, it is necessary to charge this increased equivalent input capacitance. During the charging process, even if the input voltage continues to rise, since most of the is used to charge the capacitor, this results in a slower rise in Vgs, thus forming the small plateau in Vgs that we see.

Further investigation that after changing the resistor R1 from 5K to 1K and simulating again, the small plateau becomes significantly smaller or even almost disappears. This is the MOSFET turn-on is the process of charging Cgs through R1. With a smaller R1 value, the charging time constant decreases, and the charging Cgs speeds up, allowing the MOSFET to quickly pass through the plateau stage and rapidly enter the fully conductive state. Therefore, reducing R1 can improve the, making it smaller or even disappear.